Spring 2018 Indoor Soccer Intramurals Team (left to right): Diane, Lesley, Hamed Seyedroudbari, Jose Olmedo, Hosna Qasmei, Ameen Seyedroudbari, Jose Morales
Northridge Scholars Reception (left to right): Hamed Seyedroudbari, Dr. Diane Harrison (President of CSUN)
Interns at Sony Pictures Entertainment (left to right): Galina Kaye, Hamed Seyedroudbari, Danny Nguyen, Elisa Han, Juan Neri.
Xilinx Zynq Ultrascale+ MPSoC ZCU102 development board used to prototype software and firmware used in ALR-67 RWR(radar warning receiver) during my internship at Raytheon.
Designed and implemented the data path, control path, & architecture of RISC-Y processor in SystemVerilog. Digram shows breakdown of a RISC-Y processor into smaller modules to facilitate the understanding of the overall design.
FPGA Design Lab which involved the communication between 3 RAMs and 3 FIFOs, all of different sizes. The diagram above shows the design that was programmed in VHDL. Purpose of of this comparably large design was to become introduced to FIFOs and to realize how much timing is important in the circuit's operations. Click here for a more detailed file.
Digital Lock which was an FSM implemented on as an FPGA Design Lab.