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Hybrid Microelectronics Laboratory/Class 10,000 Clean Room

. Image of the Hybrid Microelectronics Laboratory/Class 10,000 Clean Room

Lab Coordinator - Dr. Somnath Chattopadhyay

The Hybrid Microelectronics Laboratory is located in Jacaranda Hall (JD) 1101. The laboratory space is approximately 1148 square feet. This is one of the newest laboratories in the department. Its use will primarily be for conducting experiments and fabricating semiconductor devices for the solid state courses. This laboratory will be used by undergraduate and graduate students along with associated individuals from other schools and industry.

Present Activity for Device Fabrication

1 µm gate length MESFET device fabrication is in ongoing development. Doping concentration and junction depth are precisely controlled by upgraded diffusion furnace using PH 900 and PH 950 planar diffusion sources (PDS) from Saint Gobain Inc.

The photolithography process is being optimized utilizing Shipley photoresist and Karl Suss MA56 mask aligner for single layer and bi-layer and mask aligning process technology. The optimization of aluminum thin film deposition is an ongoing process to form contact pads for the source and drain.

The optimization of indium tin oxide (ITO) thin film deposition is an ongoing process to form the Schottky gate contact of the MESFET

Other Research Activity

Image of the Hybrid Microelectronics Laboratory/Class 10,000 Clean Room

Developed the silicon carbide (SiC) based ion implanted MESFET modeling for high power and high frequency amplification for satellite communication and military applications. Silicon carbide MESFET modeling showed the SiC based MESFET has the potential to deliver power approximately 80-90 watts and frequency in X – Ka band range. The modeling results also show that the device performance at such delivered power and frequency levels does not degrade up to 600 oC. The model has been developed based on the SRIM software to optimize the ion implantation impurity distribution and the results are currently being verified with Synopsys software. This research work has potential for tremendous positive impact in advancement of communication engineering and will be shortly submitted for journal publication.