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Cadence ASIC Design Laboratory

. Image of the Cadence ASIC Design Laboratory.

Lab Coordinator - Dr. Ron Mehler

The Application Specific Integrated Circuit (ASIC) lab is located in Jacaranda Hall (JD)1104. Laboratory space is approximately 3000 square feet. It has 30 Sun workstations that can accommodate 30 students and two laser printers. It supports ECE 526L (Verilog HDL: Modeling, Simulation and Synthesis Laboratory) and ECE 527L (Application Specific Integrated Circuit Development Lab).

The main software packages being run on these computers are the complete Cadence integrated circuit development suite as well as Synopsys Design Compiler, Test Compiler, Library Compiler, Static Timing Analyzer and related tools. We also have installed Vera for formal verification, in anticipation of the development of a new integrated circuit verification course.