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Links for Prospective Students

CADENCE University Program Member

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Laboratory Coordinator: Dr. Ronald Mehler - 818-677-2495 - ronald.mehler@csun.edu

Cadence Design Systems has the most comprehensive software toolsets for any type of digital IC implementation. Cadence provides end-to-end solutions for nearly any type of electronic design. Its proven products have helped companies around the world design everything from the largest electronic systems to leading-edge mixed-signal SoCs.

Cadence tools are organized into a number of featured applications. Each contains the complete set of tools regardless of the design technology needed to address that particular application. Cadence tools are also organized into the following nine standard design technologies:

  • System-level Design
  • Functional Verification
  • Emulation and acceleration
  • Synthesis/Place-and-Route
  • Analog, RF, and Mixed-Signal Design
  • Custom IC Layout
  • Physical Verification and Analysis
  • IC Packaging
  • PCB Design

Most of these tools are available for our students in both the Verilog ASIC Design Laboratory, room JD 1104, and the Senior Design Laboratory, room JD 2201.

Verilog ASIC Design Laboratory serves as a laboratory for our digital design courses. The Lab projects of ECE526 Verilog, Modeling, Simulation and Synthesis are based entirely on the use of Cadence tools. This lab is also used by our graduate students in their research.

Senior Design Laboratory is used by our senior students in designing, developing and building their senior projects.

Applications in Class

Cadence product simulators serve both ECE 340 and 440 in the JD 1566 lab. In 340, we measure diode and bipolar transistor parameters for use in breakout models. We also measure parameters for use in MOSFET breakout models. Simulations are compared to bench measurements for student designed circuits.

In ECE 440, the main focus is on accurate measurements to accurately predict the performance of amplifiers using breakout models. Student designed amplifiers are compared to simulations over voltage, time and frequency.

Cadence product simulators serve ECE 320 in the JD 1601 lab where we use historical digital circuits from the 4000 and 7400 series. Students compare bench performance to simulated timing diagrams up to a few digital variables.

Cadence product simulators serve ECE 442, 443 and 425 in the JD 1607 lab. In 442, the main focus is on accurate measurements for MOS transistors to accurately predict the performance of digital circuits ranging from inverters to 8 bit counters. Breakout models are used extensively. CMOS technology is emphasized.

In ECE 443, the main focus is on breakout models for MOSFETs to accurately predict the performance of comparator, digital to analog, and analog to digital circuits. Breakout models are used extensively. Student designed digital circuits, mainly CMOS are compared to simulations over voltage, time and frequency.

In ECE 425, microprocessor interfaces are simulated prior to bench experimentation. In this application a wide range of existing library parts are used.

Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134.